Tokyo, June 4, 2012 – Tohoku University announces today that it has used spintronics technology to develop successfully the world’s first 3-D stacked reconfigurable spin logic chip. The 3-D stacked reconfigurable spin logic chip is a key component of the ultra-high performance and ultra-low power reconfigurable spin processor that can vary a circuit’s configuration in accordance with its uses and situations. The 3-D stacked reconfigurable spin logic chip can be achieved with 3-D LSI chip stacking and on-chip SPRAMs. From the SPRAM cell evaluation, the fastest write speed of 5 ns was obtained in the circuits. Moreover, parallel reconfiguration was fully demonstrated for the 3-D stacked reconfigurable spin logic chips for the first time. Both ultrafast on-chip SPRAM and 3-D stacked structure will replace conventional 2-D LSIs and open a new era of LSIs.

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[For inquiries]

Naoki Kasai, Deputy Director

Center for Spintronics Integrated Systems, Tohoku University

TEL: +81-22-217-6115

E-mail: n-kasai@csis.tohoku.ac.jp